Dynamic device address assignment mechanism for a data processin

Details Dynamic device address assignment mechanism for a data processin Dynamic device address assignment mechanism for a data processin

1980-07-30

1983-02-08

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 930

Patent

active

043731813

ABSTRACT:
A peripheral device address assignment mechanism is described which does not require the use of plugboards or jumpers. This mechanism enables a host processor to select any desired peripheral device and set its device address to any desired value at any desired time. This is accomplished by providing each peripheral device control unit with a loadable device address register for holding the device address assigned to its peripheral device. Each device control unit is further provided with circuitry responsive to the appearance of a unique I/O command on the processor I/O bus and to the activation of a unique set of the I/O bus data lines by the processor for loading into its device address register the desired device address value as supplied thereto by the processor via the I/O bus.

REFERENCES:
patent: 4156277 (1979-05-01), Seitz et al.
patent: 4212080 (1980-07-01), Millikin
patent: 4253087 (1981-02-01), Saal
Rosenberg, "Program Controlled I/O Address Assignment", IBM Technical Disclosure Bulletin, Jun. 1973, pp. 67-68.

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