Patent
1987-11-23
1990-03-06
James, Andrew J.
357 233, 357 234, 357 41, 357 71, H01L 2978, H01L 2702, H01L 2348
Patent
active
049070487
ABSTRACT:
An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment members and a heavily doped junction is aligned with the outboard alignment members.
REFERENCES:
patent: 4258465 (1981-03-01), Yasui et al.
patent: 4347654 (1982-09-01), Allen et al.
patent: 4366613 (1983-01-01), Ogura et al.
patent: 4402761 (1983-09-01), Feist
patent: 4419809 (1983-12-01), Riseman et al.
patent: 4419810 (1983-12-01), Riseman
patent: 4488351 (1984-12-01), Momose
patent: 4503601 (1985-03-01), Chiao
patent: 4532004 (1985-07-01), Akiyama et al.
patent: 4536944 (1985-08-01), Bracco et al.
patent: 4566175 (1986-01-01), Smayling et al.
patent: 4590663 (1986-05-01), Haken
patent: 4597824 (1986-07-01), Shinada et al.
patent: 4597827 (1986-07-01), Nishitani et al.
patent: 4599118 (1986-07-01), Han et al.
patent: 4600445 (1986-07-01), Horr et al.
patent: 4769686 (1988-09-01), Horinchi et al.
patent: 4818715 (1989-04-01), Chao
patent: 4837180 (1989-06-01), Chao
Tsang, "Process for Fet With Short Channel Defined by Shallow Extensions of Drain and Source Diffusions", IBM Technical Disclosure Bulletin, vol. 25, No. 1, Jun. 1982.
Huang et al., "A Novel Submicron LDD Transistor With Inverse-T Gate Structure", Proceedings of the International Election Devices Meeting, Dec. 7-10, 1986.
Huang et al., "A New LDD Transistor With Inverse-T Gate Structure", IEEE Electron Device Letters, vol. EDL-8, No. 4., Apr. 1987.
Huang et al., "Eliminating Spacer-induced Degradations in LDD Transistors", 3rd International Symposium on VLSI Technology Systems and Application, May 1987.
Takeda, E., Kume, H., Nakagome, Y., Makino, T., Shimizu, A., and Asai, S., "An As-P.sub.(n+-n-) Double Diffused Drain Mosfet for VLSI's," IEEE Transactions on Electron Devices, vol. ED-30, No. 6, pp. 652-657, Jun. 1983.
Lee, J., Mayaram, K., and Hu, C., "A Theoretical Study of Gate/Drain Offset in LDD Mosfet's," IEEE Electron Device Letters, vol. EDL-7, No. 3, pp. 152-154, Mar. 1986.
Takeda, E., Kume, H., Toyable, T., and Asai, S., "Submicrometer MOSFET Structure for Minimizing Hot-Carrier Generation," IEEE Transactions on Electron Devices, vol. ED-29, No. 4, pp. 611-618, Apr. 1982.
Hsu, F.-C., and Grinolds, H. R., "Structure-Enhanced MOSFET Degradation Due to Hot-Electron Injection," IEEE Electron Device Letters, vol. EDL-5, No. 3, pp. 71-74, Mar. 1984.
Hui, J., and Moll, J., "Submicrometer Device Design for Hot-Electron Reliability and Performance," IEEE Electron Device Letters, vol. EDL-6, No. 7, pp. 350-352, Jul. 1985.
Tsang, P. J., Ogura, S., Walker, W. W., Shepard, J. F., and Critchlow, D. L., "Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology," IEEE Transactions on Electron Devices, vol. ED-29, No. 4, pp. 590-596, Apr. 1982.
Momose, H., Saitoh, M., Shibata, H., Maeda, T., Sasaki, H., Satoh, K. and Ohtani, T., "Performance of CMOS Circuits with LDD-Type NMOSFET's for High Density Static RAMS's," IEDM, Toshiba Corporation, Japan, pp. 304-307, 1984.
Miyamoto, J., Saitoh, S., Momose, H., Shibata, H., Kanzaki, K. and Kohyama, S., "A 1.0um N--Well CMOS/Bipolar Technology for VLSI Circuits," IEDM Toshiba Corporation, Japan, pp. 63-66, 1983.
Abend Serge
James Andrew J.
Ngo Ngan Van
Xerox Corporation
LandOfFree
Double implanted LDD transistor self-aligned with gate does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Double implanted LDD transistor self-aligned with gate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Double implanted LDD transistor self-aligned with gate will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-51290