Memory address decoding circuit for a simultaneous operation fla

Details Memory address decoding circuit for a simultaneous operation fla Memory address decoding circuit for a simultaneous operation fla

1998-09-23

1999-12-21

Le, Vu A.

Static information storage and retrieval

Floating gate

Particular connection

36518513, 36523004, 36523006, G11C 700

Patent

active

06005803&

ABSTRACT:
A decoding circuit 54 for a simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises an X-decoder 44, a lower bank decoder 58, an upper bank decoder 56, and a plurality of flexibly partitioned conductive lines coupled between the upper and lower bank decoders 56 and 58. The flexibly partitioned conductive lines 60, 62, 64, . . . 74 provide a plurality of bank address pre-decoding bits for the X-decoder 44 to row decode the memory cells along the respective word lines in the memory array 20. The memory array 20 includes a plurality of flexibly partitioned bit lines comprising first and second bit line segments to partition the memory array into upper and lower memory banks. The bit line segments in the upper and lower memory banks are coupled to two Y-decoders 32 and 34 which provide column decoding for the memory cells in the upper and lower memory banks.

REFERENCES:
patent: 5245572 (1993-09-01), Kosonocky et al.
patent: 5712823 (1998-01-01), Gillingham
patent: 5841696 (1998-11-01), Chen et al.
patent: 5847998 (1998-12-01), Van Buskirk
patent: 5867490 (1999-02-01), Chen et al.

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