Digital PLL circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

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327150, H03K 1900, H03L 7099

Patent

active

060054271

ABSTRACT:
In a digital PLL circuit, a DCO 3a comprising a full adder 33 and a delay circuit 34 accumulate a frequency control data N, to generate digital phase data ACC which periodically changes at a rate corresponding to the frequency control data N, a latch circuit 11 latches the digital phase data ACC with the aid of an input digital signal .phi..sub.in, and outputs it as a digital phase difference signal PC, and a loop filter 2 removes components in an unwanted frequency band from the digital phase difference signal PC, to form the frequency control data which is applied to the digital control oscillator means. In the digital PLL circuit, the digital phase data ACC itself, being synchronized in phase with the input digital signal .phi..sub.in, is periodically changed.

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patent: 5638010 (1997-06-01), Adams
Hikawa, H. and Mori, S., "A Digital Frequency Synthesizer with a Phase Accumulator," 1988 IEEE International Symposium on Circuits and Systems (Jun. 7-9, 1988).

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