Method and apparatus for improving fault coverage of system logi

Details Method and apparatus for improving fault coverage of system logi Method and apparatus for improving fault coverage of system logi

1991-06-19

1994-08-23

Cosimano, Edward R.

Excavating

364488, 364579, 364580, 371 226, H04B 1700

Patent

active

053413822

ABSTRACT:
A method and apparatus for improving the testability of system logic of an integrated circuit having embedded memory arrays is disclosed. The embedded memory arrays are coupled to a binary constant generation and selection circuit which is also coupled to the system logic. During a test mode, the selection circuit sends a binary constant to the system logic in lieu of normal operational data output from the memory arrays. The system logic is tested while the binary constant is continuously applied.

REFERENCES:
patent: 4481627 (1984-11-01), Beauchesne et al.
patent: 4752729 (1988-06-01), Jackson et al.
patent: 4937765 (1990-06-01), Shupe et al.
patent: 5005173 (1991-04-01), Martin
patent: 5130645 (1992-07-01), Levy
patent: 5132974 (1992-07-01), Rosales
patent: 5144230 (1992-09-01), Katoozi et al.
patent: 5202626 (1993-04-01), Pham
patent: 5254943 (1993-10-01), Momase
patent: 5289119 (1994-02-01), Schroeder
"Digital Systems Testing and Testable Design", Miron Abramovici, Melvin A. Breuer, and Arthur D. Friedman, Computer Science Press, pp. 343-346 and 364-381.

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