Wiring layout design method and system for integrated circuits

Details Wiring layout design method and system for integrated circuits Wiring layout design method and system for integrated circuits

1991-12-17

1994-08-23

Black, Thomas G.

Boots, shoes, and leggings

364488, 364489, 364490, H01L 2102, G06F 1520

Patent

active

053413105

ABSTRACT:
A wiring layout design method and system providing efficient routing of wiring paths between multiple function blocks in an integrated circuit is disclosed. Associated with the function blocks are logic service terminals (LSTs) aligned on-grid relative to the global wiring layout. The technique utilizes a locator designating a desired contact point for each on-grid LST to be connected. The contact point designation is made without restriction relative to the predetermined grid pattern of the logic service terminals. Subsequent use of a conventional global wiring layout program to generate a layout of connections between LSTs, a reformatting program connects each wired logic service terminal to its desired contact point on the associated function block using the corresponding locator.

REFERENCES:
patent: 4295149 (1981-10-01), Balyoz et al.
patent: 4484292 (1984-11-01), Hong et al.
patent: 4500963 (1985-02-01), Smith et al.
patent: 4613941 (1986-09-01), Smith et al.
patent: 4615010 (1986-09-01), Davis et al.
patent: 4615011 (1986-09-01), Linsker
patent: 4700316 (1987-10-01), Nair
patent: 4742471 (1988-05-01), Yoffa et al.
patent: 4745084 (1988-05-01), Rowson et al.
patent: 4752887 (1988-06-01), Kuwahara
patent: 4782193 (1988-11-01), Linsker
patent: 4825107 (1989-04-01), Naganuma et al.
patent: 4829014 (1989-05-01), Yerman
patent: 4849904 (1989-07-01), Aipperspach et al.
patent: 4852015 (1989-07-01), Doyle, Jr.
patent: 4855929 (1989-08-01), Nakajima
patent: 4890238 (1989-12-01), Klein et al.
patent: 4910680 (1990-03-01), Hiwatashi
patent: 5019997 (1991-05-01), Haller
patent: 5060116 (1991-10-01), Grobman et al.
Feth et al., "High-Density Cell Layout Design for VLSI Semiconductor Chips", IBM Technical Disclosure Bulletin, vol. 27, No. 11, pp. 6741-6744, 1985.
Curtin et al., "Chip-Redundant Wiring Technique", IBM Technical Disclosure Bulletin, vol. 27, No. 12, pp. 7225-7226, 1985.
Bajuk et al., "Borderless Gate Contacts for CMOS Applications", IBM Technical Disclosure Bulletin, vol. 32, No. 3B, pp. 71-73, 1989.
Ishikawa et al., "Compaction Based Custom LSI Layout Design Method", IEEE Computer Society, Nov. 18-21, 1985, IEEE International Conference on Computer-Aided Design, pp. 343-345.
Anderson et al., "Chip Design Exclusively by Programs", IBM Technical Disclosure Bulletin, vol. 32, No. 3B, pp. 417-418, 1989.
R. S. Rutter, "Method to Improve Chip Wiring", IBM Technical Disclosure Bulletin, vol. 32, No. 4B, pp. 290-293, 1989.
Dennean et al., "Wiring Machine", IBM Technical Disclosure Bulletin, vol. 24, No. 11A, pp. 5377-5383, 1982.
Berndlmaier et al., "Optimizer Chip Cell Organization", IBM Technical Disclosure Bulletin, vol. 21, No. 4, pp. 1463, 1978.
Hauge et al., "Procedure for Hierarchical Chip Physical Design", IBM Technical Disclosure Bulletin, vol. 28, No. 5, pp. 1981-1985, 1985.
Coppersmith et al., "Improved Local Wiring of Movable Terminals in VLSI Chips", IBM Technical Disclosure Bulletin, vol. 26, No. 12, pp. 6315-6317, 1984.
Kurtzberg et al., "Estimating Chip Wirability by Routing Configuration Averaging", IBM Technical Disclosure Bulletin, vol. 26, No. 5, pp. 2625-2633, 1983.

Affiliated with

Also associated with

Rating

Wiring layout design method and system for integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wiring layout design method and system for integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wiring layout design method and system for integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-507537