Reference voltage generating circuit with temperature stability

Details Reference voltage generating circuit with temperature stability Reference voltage generating circuit with temperature stability

1994-11-14

1995-07-11

Stephan, Steven L.

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

G05F 316

Patent

active

054324327

ABSTRACT:
M1 and M2, because their capacity ratio is 1:K.sub.1, have different gate-source voltages. M3 and M4, which constitute a current mirror circuit, have a capacity ratio of K.sub.2 :1. Thus, M1 and M2 are driven at a current ratio of K.sub.2 :1. As a result, the temperature dependence of mobility and that of threshold voltage can cancel each other to make it possible to realize on a CMOS integrated circuit a reference voltage generating circuit with reduced temperature dependence. As the output reference voltage, V.sub.REF will be used if a resistor R1 is present, or V.sub.REF will be used if the resistor R1 is dispensed with. The output may as well be taken out of the gate of M2 (V.sub.REF2), or out of the drain of M2 in which case the drain is provided with a resistor. Q1 and Q2, which are PNP transistors, have an emitter size ratio (Q1:Q2) of 1:K.sub.1, and their bases are commonly connected and grounded via an analog ground V.sub.AG, their collectors being also grounded. Thus Q1 and Q2 are diode-connected. P channel MOS transistors (M1 and M2) and N channel MOS transistors (M3 and M4) constitute a current mirror circuit each, and their mirror ratio (M1:M2=M3:M4) is K.sub.2 :1. In these two current mirror circuits, transistors equal in capacity (M1 and M3, and M2 and M4) are connected to each other in series.

REFERENCES:
patent: 4683414 (1987-07-01), Moore
patent: 5045773 (1991-09-01), Westwick et al.
patent: 5144223 (1992-09-01), Gillingham
Low Temperature Coefficient CMOS Voltage Reference Circuits IEICE Trans. Fundamentals, vol. E77-A, Feb. 1994.
Blauschild et al, "An NMOS Voltage Reference", IEEE International Solid-State Circuits Conference, Feb. 1978, pp. 50-51.

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