Low voltage, cascoded NTL based BiCMOS circuit

Details Low voltage, cascoded NTL based BiCMOS circuit Low voltage, cascoded NTL based BiCMOS circuit

1992-08-10

1994-08-23

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307456, 307448, H03K 1716, H03K 19094

Patent

active

053410424

ABSTRACT:
A BiCMOS circuit including an NFET transistor connected as a diode is disclosed. The NFET transistor provides a threshold level for sourcing current. A PFET transistor and a clamping diode are connected in parallel to serve as a current path to the base of a bipolar emitter follower transistor. The emitter follower transistor and an NFET transistor act as pull-up and pull-down devices at the output stage. The NFET-diode turns off the current in the logic network as well as in the output buffer when the inputs are at a low logic level. As a result, the power consumed by this NTL based BiCMOS circuit is lower compared to that of an ECL based BiCMOS circuit. Also the drawbacks of a conventional NTL circuit, low noise immunity and signal degradation, are eliminated because the NFET-diode serves as a reference level for input signals. An additional embodiment wherein CMOS logic is cascoded with the existing bipolar logic to allow a higher logic function is also disclosed. The circuit of this invention can provide a single-phase output which is compatible with a low-voltage ECL/BiCMOS signal.

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