Random access memory cell with implanted capacitor region

Details Random access memory cell with implanted capacitor region Random access memory cell with implanted capacitor region

1989-03-02

1992-12-01

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437170, 437919, H01L 2170

Patent

active

051680750

ABSTRACT:
A N-channel MOS random access memory of the one transistor type is disclosed. The cell utilizes an ion implanted area beneath the capacitor dielectric to permit lower bias voltages on the capacitor. In one example, two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitor, and the other for the gate of the MOS transistor and to connect the gate to the bit select line. The capacitor dielectric may be formed of thermal SiO.sub.2 which is about half as thick as the gate insulator of the MOS transistor in the cell. In another example, a single-level poly cell uses an implanted region for the same purpose; the capacitor dielectric is the same thickness as the MOS gate insulator so the lower bias voltage functions to reduce stress failures of the dielectric.

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