Process for making a contact betwen a capacitor electrode dispos

Details Process for making a contact betwen a capacitor electrode dispos Process for making a contact betwen a capacitor electrode dispos

1994-08-04

1995-07-11

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 52, 437919, H01L 218242

Patent

active

054321158

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

To design 16M and 64M DRAM circuits, storage cells are needed which have a small space requirement and can be disposed in a substrate with high packing density. Such a storage cell concept is known in the form of the ISTT (Isolated Stack in Trench) DRAM cell and of the BSCC (Buried stacked capacitor cell). This storage cell has a transistor and a capacitor. The capacitor is disposed with both capacitor electrodes and the dielectric in a trench, the capacitor being insulated from the substrate by an oxide layer disposed at the trench surface (see, for example, J. Dietl et al., ESSDERC 90, pages 465 to 468).
In this cell concept it is necessary to make an electrical contact between the transistor source/drain region and the capacitor electrode, which is disposed in the trench and insulated from the substrate and on which the charge corresponding to the information is stored. Two possibilities of making the contact are disclosed in the literature (see J. Dietl, ESSDERC 90, pages 465 to 468):
After the trench has been etched, its surface is provided with an SiO.sub.2 layer. The trench is then filled with photoresist. The size of the contact on the edge of the trench adjacent to the transistor is defined by re-exposing the photoresist down to the specified depth. This exposure of the photoresist depth is only poorly reproducible. In the process, variations of around 1 .mu.m occur. With this process it is therefore not possible to open the contact only with respect to the subsequent source/drain region. A contact opening to parts of the substrate disposed underneath the source/drain region also inevitably results. This results in punch-through and leakage currents.
Alternatively, a shallow trench etching is first carried out. An Si.sub.3 N.sub.4 spacer is formed at the edge adjacent to the source/drain region. A further trench etching follows in which the final depth of the trench is reached. The surface of the trench is then provided with an SiO.sub.2 layer. The contact to the source/drain region is opened by stripping the Si.sub.3 N.sub.4 spacer. The depth of the contact is established by means of the depth of the shallow etching. In the shallow etching, it is necessary to ensure that the substrate is not laid bare on the side of the trench produced which is remote from the source/drain region and at which the storage cell is insulated from adjacent active regions by a field-oxide region. If this is not so, a contact to the substrate, which impairs the insulation between the cells, is produced on this side.
In both the known processes, a further photolithographic procedure is needed to define the position of the contact in addition to the photo-lithographic procedure for patterning the trench.


SUMMARY OF THE INVENTION

The invention therefore proceeds from the problem of providing a process for making a contact between a capacitor electrode disposed in a trench and an MOS transistor source/drain region disposed outside the trench, in which process the depth of the contact can be satisfactorily controlled and, at the same time, reliable insulation is ensured between adjacent active regions.
This problem is solved, according to the invention, by a process having the following steps. At least one field-oxide region is formed in a substrate Si to the side of the source/drain region as insulation from adjacent active regions in the substrate. A trench mask is produced which defines the position of the trench to the side of the source/drain region on the side of the field-oxide region adjacent to the source/drain region such that the trench is arranged between the source/drain region and the field-oxide region. The trench mask leaves the field-oxide region partially uncovered on the side adjacent to the source/drain region. A photoresist is arranged on the surface of the trench mask. A first etching is carried out to produce the trench to a first depth in the substrate, which attacks the substrate selectively on photoresist and the field-oxide region, so that the trench mask covered wi

REFERENCES:
patent: 4734384 (1988-03-01), Tsuchiya
patent: 4967248 (1990-10-01), Shimizu
patent: 4999312 (1991-03-01), Yoon
patent: 5262002 (1993-11-01), Grewal et al.
"Technologies for Megabit DRAMs", Wolfgang Muller et al, Archiv Fur Elektronik und Ubertragungstechnik, vol. 44, No. 3, May 1990, pp. 200-207.
"Buried Stacked Capacitor Cells for 16M and 64M DRAMS", J. Dietl et al, ESSDERC 90, Sep. 1990, pp. 465-468.

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