Method for fabricating self-aligned polysilicon contacts on FET

Details Method for fabricating self-aligned polysilicon contacts on FET Method for fabricating self-aligned polysilicon contacts on FET

1994-09-19

1995-07-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 57, 437162, H01L 218238

Patent

active

054321050

ABSTRACT:
Improved N-channel and P-channel field effect transistor device structure having self-aligned polysilicon pads contacts and a process for making such devices has been achieved. The doped polysilicon pad contact are formed over the source/drain areas of the field effect transistors and are used to form shallow self-aligned diffused contact to the source/drain areas. These polysilicon pads provide a low resistance ohmic contacts that are free from implant damage that would otherwise cause increased junction leakage current and are free of metal spiking at the source/drain area perimeter that would cause metal contact to substrate shorts. The increased area of the polysilicon pads over the source/drain area allows for relaxed design ground rule for the contact openings, making for a more manufacturable process for Ultra Large Scale Integration applications.

REFERENCES:
patent: 4717684 (1988-01-01), Katto et al.
patent: 4824796 (1989-04-01), Chiu et al.
patent: 4902640 (1990-02-01), Sachitano et al.
patent: 5015594 (1991-05-01), Chu et al.

Affiliated with

Also associated with

Rating

Method for fabricating self-aligned polysilicon contacts on FET does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating self-aligned polysilicon contacts on FET , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating self-aligned polysilicon contacts on FET will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-503090