Fishing – trapping – and vermin destroying
Patent
1994-10-07
1995-07-11
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 89, 437162, 437909, 148DIG10, H01L 21331
Patent
active
054321042
ABSTRACT:
A method of fabricating a vertical bipolar semiconductor device includes a step of forming an N.sup.- -type silicon epitaxial layer which constitutes a part of a collector region and a P.sup.+ -type polycrystalline silicon film which functions as a base lead-out electrode. The silicon epitaxial layer and the polycrystalline silicon film are insulated by a silicon oxide film which is a sufficiently thick insulating film, covers the silicon epitaxial layer and has an opening. In this opening, by selective growth of a first and a second semiconductor film and ion implantation using a first insulating film spacer, there are formed a P.sup.- -type single crystal silicon layer, a P.sup.+ -type polycrystalline silicon film, a P.sup.+ type single crystal silicon layer (intrinsic base region), a P.sup.+ -type polycrystalline silicon film, and an N-type single crystal silicon layer. It is possible to reduce the parasitic capacitance between the base region and the collector region without sacrificing the enhancement of the cut-off frequency f.sub.T.
REFERENCES:
patent: 4824799 (1989-04-01), Komatsu
patent: 4851362 (1989-07-01), Suzuki
patent: 5039624 (1991-08-01), Kadota
patent: 5198373 (1993-03-01), Yoshino
patent: 5204276 (1993-04-01), Nakajima et al.
patent: 5217909 (1993-06-01), Bertagnolli
patent: 5294558 (1994-03-01), Subbanna
patent: 5296391 (1994-03-01), Sato et al.
patent: 5320972 (1994-06-01), Wylie
Hearn Brian E.
NEC Corporation
Nguyen Tuan
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