Method of making a vertical gate transistor with low temperature

Details Method of making a vertical gate transistor with low temperature Method of making a vertical gate transistor with low temperature

1993-08-30

1994-08-23

Fourson, George

Fishing, trapping, and vermin destroying

437909, 437915, H01L 21265

Patent

active

053407598

ABSTRACT:
A field effect transistor (FET) with a vertical gate and a very thin channel sandwiched between source and drain layers. In a preferred embodiment of the invention, the FET is formed on a silicon on insulator (SOI) substrate with the silicon layer serving as the first layer (e.g., the source layer). A low temperature epitaxial (LTE) process is used to form a very thin (e.g., 0.1 .mu.m) channel, and a chemically vapor deposited polysilicon layer forms the top layer (e.g., the drain layer). An opening is etched through the three layers to the insulator substrate and its wall is oxidized, forming a gate oxide. Polysilicon is deposited to fill the opening and form the vertical gate.

REFERENCES:
patent: 4914051 (1990-04-01), Huie et al.
patent: 4970173 (1990-11-01), Robb
patent: 4983535 (1991-01-01), Blanchard
patent: 5155052 (1992-10-01), Davies
patent: 5250449 (1993-10-01), Kuroyanagi et al.
patent: 5273921 (1993-12-01), Neudeck et al.

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