LDD MOS device having an element separation region having an ele

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357 233, 357 2314, 357 52, H01L 2910, H01L 2978, H01L 2934

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049981617

ABSTRACT:
In an element forming region (10) of a semiconductor substrate (1), there are provided a gate electrode (2), sidewall insulating films (4), impurity diffusion regions (5a and 5b) of a lower concentration having their one ends are overlapped with the side sections of the gate electrode (2), and impurity diffusion regions (6a and 6b) of a higher concentration having their one ends are overlapped with the side sections of the sidewall insulating films (4). In an element isolation region (7) of the semiconductor substrate, there are formed an electrostatic screening electrode (31) for element isolation and an insulating film (30) substantially enclosing the electrostatic screening electrode. By employing the electrostatic screening electrode (31) for element isolation in the LDD MOS transistor, there is obtained a semiconductor device of high performance and reliability which is free from intrusion of impurities from the element isolation region.

REFERENCES:
patent: 4868617 (1989-09-01), Chiao et al.
Kroell et al., "Field Shield MOS Transistor with Self-Aligned Gate", IBM Tech. Disc. Bulletin, vol. 16, No. 6, Nov. 1973, pp. 1860-1861.
Paul J. Tsang et al., "Fabrication of High Performance LDDFET's with Oxide Sidewall Spacer Technology", IE.sup.3 Transactions Electron Device, vol. ED-29, No. 4, Apr. 1982, pp. 590-596.

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