Method of fabricating an isolated gate JFET

Details Method of fabricating an isolated gate JFET Method of fabricating an isolated gate JFET

1984-04-13

1985-01-29

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, H01L 2980, H01L 2702, H01L 2704

Patent

active

044956940

ABSTRACT:
A JFET having the top gate isolated from the bottom gate by an annulus source region and thin channel region and a top gate ohmic contact region isolated from the bottom gate by a deep isolation region. The isolation region and the top gate contact region are exterior the active channel region.

REFERENCES:
patent: 3223904 (1965-12-01), Warner et al.
patent: 3649385 (1972-03-01), Kobayashi
patent: 4143392 (1979-03-01), Mylroie
patent: 4176368 (1979-11-01), Compton
patent: 4187514 (1980-02-01), Tomisawa et al.
patent: 4322738 (1982-03-01), Bell et al.
patent: 4395812 (1983-08-01), Bergeron et al.
"JFET-Transistor Yields Device With Negative Resistance", John A. Porter, IEEE Transactions on Electron Devices, Sep. 1976, pp. 1098-1099.

Affiliated with

Also associated with

Rating

Method of fabricating an isolated gate JFET does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating an isolated gate JFET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating an isolated gate JFET will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-499424