Manufacture of a split-gate EPROM cell using polysilicon spacers

Details Manufacture of a split-gate EPROM cell using polysilicon spacers Manufacture of a split-gate EPROM cell using polysilicon spacers

1991-02-05

1991-11-05

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437 52, 437195, H01L 21265

Patent

active

050631721

ABSTRACT:
The present invention provides an integrated circuit fabrication method that utilizes a conductive spacer to define the gate length of the series select transistor in a split-gate memory cell. Since the length of the spacer can be controlled with great precision using existing integrated circuit process technologies, misalignment problems associated with the prior art split-gate cells are eliminated.

REFERENCES:
patent: 4639893 (1987-01-01), Eitan
patent: 4794565 (1988-12-01), Wu et al.
patent: 4808261 (1989-02-01), Ghidini et al.
patent: 4861730 (1989-08-01), Hsia et al.
Ali et al., "A New Staggered Virtual Ground Away Architecture Implemented in a 4Mb CMOS EPROM", 1989 VLSI Circuits Conference, Tokyo, Japan.
G. Perlegos et al., "A 64K EPROM Using Scaled MOS Technology", ISSSCC Digest of Technical Papers, 1980 IEEE International Solids State Circuits Conference, pp. 142-143.

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