Sixteen-bit programmable pipelined arithmetic logic unit

Details Sixteen-bit programmable pipelined arithmetic logic unit Sixteen-bit programmable pipelined arithmetic logic unit

1989-01-30

1990-06-05

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 700

Patent

active

049319744

ABSTRACT:
For use in calculating discrete, fast fourier transformations, an arithmetic logic unit includes a number of multiplexers and registers, which, in combination, form a configurable pipeline, register ("A"), that functions as a four-deep pipeline register, as two, two-deep, pipeline registers, or as four separate registers, to latch and "delay" the parameter represented by the state of signals externally developed on a "DA" bus; the combination of a funnel shifter, a merge logic unit and a multiplexer; a unit for "bit-reverse order" addressing; and a unit for "rounding off" certain results.

REFERENCES:
patent: 4760517 (1988-07-01), Miller et al.
patent: 4760544 (1988-07-01), Lamb
K. Kloker, "The Motorola DSP56000 Digital Signal Processor", IEEE Micro, Dec. 1986, pp. 29-48.
G. Frantz et al., "The Texas Instruments TMS320C25 Digital Signal Microcomputer", Dec. 1986, IEEE Micro, pp. 10-28.
J. Lin et al., "High Performance Fixed-Point Fast Fourier Transform Processor", Integrated Device Technology, Inc. Application Note, Oct. 1988, pp. 1-15.

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