Static ram cell with trench pull-down transistors and buried-lay

Details Static ram cell with trench pull-down transistors and buried-lay Static ram cell with trench pull-down transistors and buried-lay

1989-07-25

1991-03-05

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 38, 437 47, 437 60, 437203, 437228, H01L 2170

Patent

active

049977830

ABSTRACT:
Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned polysilicon p-channel pull-up transistors without appreciably enlarging the cell area.

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Ghandhi, "ULSI Fabrication Principles", 1983, pp. 593-595.
Vonshney, "Self-Aligned VMOS Structure using Reactive ion etching", IBM TD13, vol. 22, Jan. 80, pp. 3705-3706.

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