Overflow detection for a decimal arithmetic unit

Details Overflow detection for a decimal arithmetic unit Overflow detection for a decimal arithmetic unit

1981-07-10

1984-03-13

Malzahn, David H.

Boots, shoes, and leggings

G06F 748

Patent

active

044371659

ABSTRACT:
A data processing apparatus for performing decimal arithmetic operation with the aid of a decimal arithmetic unit having an operation width corresponding to a plurality of bytes. Length value of an operand which is to undergo arithmetic operation of the decimal arithmetic unit is held in an operand length register, while a byte position which constitutes the least significant position in the arithmetic operation is held in an operand point register. An overflow detection controlling circuit generates a control signal in accordance with the contents in both the registers. An overflow detecting circuit detects presence or absence of an overflow by checking a particular byte contained in the output of the decimal arithmetic unit, the particular byte being designated by the control signal produced from the overflow detection controlling circuit.

REFERENCES:
patent: 4021655 (1977-05-01), Healey et al.
patent: 4161784 (1979-07-01), Cushing et al.
patent: 4224676 (1980-09-01), Appelt
patent: 4301514 (1981-11-01), Eifuku et al.
Rosenfeld, "Variable-Width Adder for Microprogrammed Computers Used for Emulation", IBM Technical Disclosure Bulletin, vol. 15, No. 4, Sep. 1972, pp. 1149-1150.

Affiliated with

Also associated with

Rating

Overflow detection for a decimal arithmetic unit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Overflow detection for a decimal arithmetic unit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Overflow detection for a decimal arithmetic unit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-495811