Boots – shoes – and leggings
Patent
1990-10-05
1993-09-07
Fleming, Michael R.
Boots, shoes, and leggings
395425, 395725, 364240, 3642405, 3642426, 3642427, 36424292, 364264, 3642646, 3642705, 364DIG1, G06F 900
Patent
active
052437027
ABSTRACT:
A multiprocessor system includes a plurality of central subsystem (CSS) units, a plurality of memory units and input/output units which connect in common to a system bus for transferring requests between a pair of units on a priority basis defined by a distributed bus priority network included as part of the system bus. A private bus (P bus) connects all of the CSS units and memory units in common for high speed block data transfers. Each CSS unit includes input circuits which couple to the priority network for detecting when the system bus is in an idle state. P bus logic circuits couple to the P bus and generate a transfer request in response to a request from its CSS unit only when the P bus is detected to be in an idle state. The idle signals from both buses are used to generate a system bus request for P bus access only when both buses are in an idle state so as to eliminate the need to contend for system bus use.
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European Search Report for corresponding EPO patent application 91116755.9, transmitted in a Communication dated Jul. 14, 1992.
Barlow George J.
Smith Donald L.
Bull HN Information Systems Inc.
Driscoll Faith F.
Fleming Michael R.
Hafiz Tarig R.
Solakian John S.
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