Electrical pulse counters – pulse dividers – or shift registers: c – Counting or dividing in incremental steps – Charge storage
Patent
1992-06-04
1993-09-07
Sikes, William L.
Electrical pulse counters, pulse dividers, or shift registers: c
Counting or dividing in incremental steps
Charge storage
377 94, 377 96, 307227, H03K 2100
Patent
active
052436373
ABSTRACT:
A clock stability circuit (10, 20, 30, 40) assures stable clock generator operation after oscillator start-up, such as during re-entry after a low-power Halt mode in a microprocessor or microcomputer. The clock stability circuit detects stable clock cycles that transition between a selected high amplitude threshold (near VDD) and a selected low amplitude threshold (near VSS), and provides a clock stable signal after a selected number of stable clock cycles, indicating that the oscillator has stabilized. The clock stability circuit includes four modules: input sampler (10), pulse generator (20), pulse counter (30) and control logic (40). The input sampler module includes CMOS NAND gates (11, 14) respectively fabricated with p
-channel ratios to provide a CLOCK A signal that transitions at the selected high amplitude threshold of an oscillator cycle, and a CLOCK B signal that transitions at the selected low amplitude threshold. The pulse generator module (20) functions as a modified edge-triggered D flip-flop (21, 23) that triggers in response to paired transitions of CLOCK A and CLOCK B (indicating that the oscillator clock has cycled through both the high and low amplitude thresholds), generating a transition pulse. The pulse counter module (30) includes a pulse counter capacitor (Cl) and a pulse detection transistor (31) that is turned on during each transition pulse to provide a charging path for the pulse counter capacitor, thereby incrementally charging the pulse counter capacitor in response to transition pulses. When the pulse counter capacitor (Cl) is charged to a level corresponding to the receipt of a selected number of transition pulses, a Schmitt trigger circuit (34) is activated to provide a CLOCK STABLE signal, indicating that the oscillator clock has provided a selected number of stable clock cycles. The control logic module (40) provides ENABLE, /CHARGE and DISCHARGE signals that control operation of the clock stability circuit in a microcomputer during Halt, Start and Run modes.
REFERENCES:
patent: 3474235 (1969-10-01), Singer
patent: 3714587 (1973-01-01), Lindsey et al.
patent: 4200812 (1980-04-01), Fichter
patent: 5034624 (1991-07-01), Flaherty et al.
Flaherty Edward H.
Van Lehn David A.
Barndt B. Peter
Donaldson Richard L.
Ouellette Scott A.
Sikes William L.
Texas Instruments Incorporated
LandOfFree
Apparatus and method for assuring stable clock generator during does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for assuring stable clock generator during , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for assuring stable clock generator during will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-493792