Flexible imbedded test system for VLSI circuits

Details Flexible imbedded test system for VLSI circuits Flexible imbedded test system for VLSI circuits

1989-03-23

1990-06-05

Eisenzopf, Reinhard J.

Excavating

324158R, 371 151, G01R 3128, G06F 1100

Patent

active

049317229

ABSTRACT:
A logic chip contains a plurality of ranks of flip-flops with combinational logic elements connected in between the flip-flop ranks. Each flip-flop has at least two distinct data paths. The first path is for the normal passage of data to combinational logic units following the rank of flip-flops, and the second path is a test path which is connected directly with the next rank of flip-flops. Operands may be shifted in parallel to bypass combinational logic units and may be directed to selected combinational logic for test purposes. The flip-flops in a rank may be serially scanned or operate in parallel to send specific operands through selected combinational logic units. It is adaptable to custom or semi-custom VLSI chip design and it teaches that any "component" (for example, a logic unit or a single element) may be tested individually using two data paths (one for test and one for operation or normal data). The test data output can be transmitted in parallel between the flip flop ranks, or it can go serially through the flip flop components of a given rank.

REFERENCES:
patent: 4244048 (1981-01-01), Tsui
patent: 4357703 (1982-11-01), Van Brunt
patent: 4527249 (1985-07-01), Van Brunt
patent: 4701920 (1987-10-01), Resnick
patent: 4701922 (1987-10-01), Kuboki
patent: 4764926 (1988-08-01), Knight
Built-In Self-Test Techniques, E. J. McCluskey, Apr., 1985, IEEE Design & Test, pp. 21-28.
Built-In Self-Test Structures, E. J. McCluskey, Apr. 1985 IEEE Design & Test, pp. 29-36.
Testing Semi-Custom Logic, E. J. McCluskey, Sep. 1985, Semiconductor International, pp. 118-123.

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