Semiconductor integrated circuit device having power down mode

Details Semiconductor integrated circuit device having power down mode Semiconductor integrated circuit device having power down mode

1988-10-07

1990-03-06

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307465, 3072721, 36518903, 365227, G11C 1140

Patent

active

049068628

ABSTRACT:
A semiconductor integrated circuit device has a plurality of terminals, an internal circuit for receiving input signals from the terminals and for outputting output signals to the terminals, where the internal circuit is enabled by a chip enable signal and disabled by a chip disable signal, a non-volatile memory for storing a pin select signal which designates at least a selected one of the terminals as a chip enable control terminal for receiving a control signal which has a first logic level when instructing a power down mode of the semiconductor integrated circuit device, and a buffer part coupled to the terminals and the non-volatile memory for generating the chip enable signal and the chip disable signal responsive to the pin select signal and the control signal. The buffer part generates the chip enable signal when the control signal received by the selected one terminal has a second logic level and generates the chip disable signal when the control signal received by the selected one terminal has the first logic level to thereby set an operation mode of the semiconductor integrated circuit device to the power down mode.

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Sau-Ching Wong et al., "Novel Circuit Techniques for Zero-Power 25-ns CMOS Erasable Programmable Logic Devices (EPLD's)", IEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct., 1986.

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