Logic transfer circuit employing MOS transistors

Details Logic transfer circuit employing MOS transistors Logic transfer circuit employing MOS transistors

1976-06-14

1977-12-13

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307208, 307221C, 307224C, 307251, 307279, 307DIG1, H03K 1908, H03K 1920, H03K 3353, G11C 1900

Patent

active

040631133

ABSTRACT:
This relates to an MOS logic synchronizing circuit operating with a single phase clock waveform. A logic inverter has two parallel-connected switching MOST's, the gate of one (M4) being connected to clock and the gate of the other (M2) being coupled to the logic input via the source-drain path of a third MOST (M1) whose gate is connected to clock. Input signal change is delayed by a full clock period.

REFERENCES:
patent: 3593036 (1971-07-01), Ma et al.
patent: 3870897 (1975-03-01), Hatsukano et al.

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