High speed tuning system

Details High speed tuning system High speed tuning system

1976-10-21

1978-01-24

Griffin, Robert L.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

325464, 325470, 358193, H04B 116

Patent

active

040706290

ABSTRACT:
A two mode tuning system includes counters for determining system tuning by counting the LOF, a channel number comparator comparing the derived channel tuning information with a desired channel number and a PLL including a phase comparator for comparing equality pulses from the channel number comparator with a reference frequency. In the first mode the system tunes to a single frequency and in the second it tunes within a frequency window. Tuning cycle control means initiate the single frequency mode in response to a channel number input or an out-of-window tuning indication and the system switches to the tuning window mode about 200ms later. Initially tuning to the "center of the tuning window" relaxes the AFC requirements for a wide window system. The tuning cycle control means also provide for initially overriding the phase comparator and PLL to drive the oscillator at "full ramp" until system tuning is driven past the frequency corresponding to the input channel number. Then, the single frequency PLL mode is initiated.

REFERENCES:
patent: 3913020 (1975-10-01), Van Anrooy
patent: 3943449 (1976-03-01), Hendrickson et al.
patent: 3962640 (1976-06-01), Bomba

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