Synchronizer and synchronization system for a multiple computer

Details Synchronizer and synchronization system for a multiple computer Synchronizer and synchronization system for a multiple computer

1980-02-05

1982-05-18

Thomas, James D.

Boots, shoes, and leggings

371 47, G06F 1116, G06F 1516

Patent

active

043308260

ABSTRACT:
The invention is a synchronizer for synchronizing the operation of the computers in a multiple computer system. One synchronizer is associated with each computer, and it regularly generates signals to initiate the operations in its own computer which must be synchronized among the computers. The synchronizer comprises a start synchronizer module (458), a sampling data table including a sampling timer (460), a check sampling timer module (464), and a find sampling number agreement module (466). The sampling period timer times a sampling period having a predetermined time interval. At the end of each sampling period, the check sampling timer module sends a sampling number message containing a new sampling number. The find sampling number agreement module (466) generates a voted sampling number when sampling number messages received from like synchronizers in a predetermined number of computers contain the same sampling number. When a voted sampling number is obtained, the synchronizer generates a signal initiating in its own computer the operations which are to be synchronized among the computers. Also, the remaining time in the sampling period timer is adjusted to synchronize its period with like sampling period timers in the other computers. When no voted sampling number is obtained, the start synchronizer module (458) is enabled to restart the synchronizer.

REFERENCES:
patent: 3602900 (1971-08-01), Delaigue
patent: 3761884 (1973-09-01), Avsan
patent: 3932847 (1976-01-01), Smith
patent: 4229792 (1980-10-01), Jensen
"Sift: The Design and Analysis of a Fault-Tolerant Computer for Aircraft Control", Wensley et al., Proceedings of the IEEE, vol. 66, No. 10, Oct. 1978, pp. 1240-1254.
"Pluribus-An Operational Fault-Tolerant Multiprocessor", Katsuki et al., Proceedings of the IEEE, vol. 66, No. 10, Oct. 1978, pp. 1146-1159.

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