Universal arrangement for the exchange of data between the memor

Details Universal arrangement for the exchange of data between the memor Universal arrangement for the exchange of data between the memor

1979-08-08

1982-05-18

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 306

Patent

active

043308244

ABSTRACT:
An interface for the exchange of data between memories and processing devices of a computer, which interface does not depend on any particular technology of the processing and memory units and which is readily adaptable to units having different timing for the signals exchanged. The interface employs asynchronous dialog signals, with adjustable timing provided by delay devices such as delay lines. The initiation of a memory cycle involves two asynchronous signals: a memory cycle request signal output by a portion of the interface included within the processing unit, and a cycle acknowledge signal output by a portion of the interface included within the memory unit and transmitted back to the processing unit to indicate that the requested memory cycle has in fact started. Another pair of asynchronous dialog signals are involved in a memory reading operation: a data ready signal output by the portion of the interface included within the memory unit, and a reading finished signal output by the portion of the interface included within the processing unit to indicate that the processing unit is finished with the data. A similar pair of asynchronous dialog signals are involved in a memory writing operation: a write initiate signal output by the processor, and a writing finished signal returned by the memory unit. Similar interface arrangements may be provided for data exchanges between processors.

REFERENCES:
patent: 3237169 (1966-02-01), Hartwig et al.
patent: 3818459 (1974-06-01), Vrablik
patent: 4099231 (1978-07-01), Kotok et al.

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