Process for preparing semiconductor device by use of a flattenin

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

437 33, 437 46, 148DIG123, H01L 21225

Patent

active

052428583

ABSTRACT:
A process for preparing a semiconductor device comprises exposing at least a part of the main surface of a semiconductor substrate, forming a layer comprising the same main component as the above substrate, forming a flattening agent layer on the surface of said layer, removing the above layer and the flattening agent layer at the same time and injecting an impurity after said removing step.

REFERENCES:
patent: 4624864 (1986-11-01), Hartmann
patent: 4707456 (1987-11-01), Thomas et al.
patent: 4728620 (1988-03-01), Jeuch
patent: 4780429 (1988-10-01), Roche et al.
patent: 4939154 (1990-07-01), Shimbo
J. Electrochem. Soc., vol. 136, No. 6, Jun. 1989, pp. 1777-1781, Sato et al. "Enhanced Boron Diffusion Through Thin Silicon Dioxide etc.".
Solar Cells, vol. 20, No. 1, Feb. 1987, pp. 51-57, Sinke et al., "A Comparison Between Excimer Laser and Thermal Annealing etc.".
J. Appl. Phys., vol. 65, No. 10, May 1989, pp. 4036-4039, Wu et al. "Retardation of Nucleation Rate For Grain Size etc.".
J. Electrochem. Soc., vol. 135, No. 4, Apr. 1988, pp. 974-979, Cole et al. "Thin Epitaxial Silicon Regrowth etc.".
J. Electrochem. Soc., vol. 134, No. 7, Jul. 1987, pp. 1771-1777, Noguchi et al. "Advanced Superethin Polysilicon Film etc.".
Appl. Phys. Let., vol. 45, No. 8, Oct. 1984, pp. 910-912, Quach et al., "Solid phase epitaxy of polycrystalline silicon films etc.".
Pat. Abs. JP. vol. 13, No. 503, Nov. 13, 1989 and JP-A-120193.
Pat. Abs. JP. vol. 9, No. 203, Sep. 17, 1985 and JP-A-60084825.
Proc. IEEE 1988 Bipolar Circuits & Technology Meeting, Sep. 1988, pp. 132-135, van Schravendijk, "Thin Base Formation etc.".
IBM Technical Disclosure Bulletin, vol. 32, No. 10A, Mar. 1990, pp. 90-91; "In Situ Deposition, Planarization, and Etching of Polysilicon".
IBM Technical Disclosure Bulletin, vol. 32, No. 4A, Sep. 1989, pp. 367-370; "Process For Low Resistivity CoSi2 Contact To Very Shallow N-P Junction".

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Process for preparing semiconductor device by use of a flattenin does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for preparing semiconductor device by use of a flattenin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for preparing semiconductor device by use of a flattenin will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-487603

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.