Method of fabricating field effect transistors having self-regis

Details Method of fabricating field effect transistors having self-regis Method of fabricating field effect transistors having self-regis

1976-06-30

1977-07-12

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

148175, 148187, H01L 21265

Patent

active

040351980

ABSTRACT:
A method of fabricating a field effect transistor (FET) wherein a self-registered or misregistration tolerant electrical connection is provided between the gate electrode and a metallic interconnection line. The method involves a unique structure which includes a thick deposited oxide insulation layer and an etch stopping layer over doped silicon source and drain regions, over polysilicon gate electrode regions, and over field isolation regions. The etch stopping layer facilitates fabrication of a self-registering electrical connection between the gate electrode and a metallic interconnection line wherever desired. The thick deposited oxide layer provides reduced capacitive coupling between the insulated regions and the metallic interconnection line when compared to known self-registered gate contacting methods that employ only thermally grown oxide insulation. The method also includes the provision for controlling the removal of insulation over the gate electrode wherever desired without seriously degrading the insulation over other parts of the structure. The disclosed method further relates to fabricating an integrated circuit containing FETs having a self-registered electrical connection between the gate electrode and the metallic interconnection line, the gate electrode self-aligned with respect to the source and drain regions, and wherein FETs of the integrated circuit have: a channel region; a gate insulator; an electrically conductive gate electrode; source and drain regions; thick insulation over the source and drain and over the gate electrode except in the contact areas; field isolation or field shield regions between FETs of the integrated circuit; metallic-type high electrical conductivity interconnection line; and self-registering electrical connection between the gate and the interconnection line.

REFERENCES:
patent: 3899363 (1975-08-01), Dennard et al.
Kalter et al., "Self-Aligning Metal to Polysilicon Contacts," IBM Tech. Discl. Bull., vol. 14, No. 10, Mar. 1972, p. 3176.
Rideout, "Masking for One-Device Cell Memories Using Self-Registering Metal-to-Polysilicon Contacts," IBM T.D. B., vol. 17, No. 9, 2/1975, pp. 2802-2804.

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