Method for fabricating complementary field effect transistor dev

Details Method for fabricating complementary field effect transistor dev Method for fabricating complementary field effect transistor dev

1983-06-29

1984-03-13

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29578, 148187, 357 42, H01L 21265

Patent

active

044358962

ABSTRACT:
Disclosed is an eight-mask twin-tub CMOS process which forms contiguous p- and n-tubs in a relatively lightly doped bulk region in a self-aligned manner using a single masking step. The process also forms the sources and drains of the p- and n-channel transistors with a single masking step by first nonselectively implanting p-type impurities into all source and drain regions and then selectively implanting n-type impurities into only the source and drain regions of the n-channel transistors in amounts sufficient to overcompensate the p-type impurities therein.

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Proceedings of the 10th Conference on Solid State Devices, Tokyo, 1978; Japanese Journal of Applied Physics, vol. 18 (1979) Supplement 18-1, pp. 73-78; "High Packing Density, High Speed CMOS (Hi-CMOS) Device Technology," Y. Sakai, T. Masuhara, O. Minato, and N. Hashimoto.
1981 IEEE International Solid-State Circuits Conference; pp. 14 and 15; "H-i-CMOSII 4K Static RAM," O. Minato, T. Masuhara, T. Sasaki, Y. Sakai and K. Yoshizaki.

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