Address buffer circuit

Details Address buffer circuit Address buffer circuit

1981-03-16

1983-08-02

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307578, 307581, 365203, 365205, 365230, H03K 3356, G11C 700

Patent

active

043968457

ABSTRACT:
An address buffer circuit for comverting an address signal (A.sub.i) of a TTL level into an address signal (A) of a MOS level an its inverted signal (A) comprising: a pre-amplifier (P-AMP) for receiving the address signal having a TTL level; a main amplifier (M-AMP) comprising a flip-flop (FF.sub.3), a circuit for defining the operation of the flip-flop (FF.sub.3); and an output circuit (OUT) comprised of another flip-flop (FF.sub.4) for producing the address signals of a MOS level. In the pre-amplifier, a depletion type transistor (Q.sub.34) is used as a reference constant current source, which is independent of a power supply voltage (V.sub.DD), for the two values of the address signal of a TTL level.

REFERENCES:
patent: 4110841 (1978-08-01), Schroeder
patent: 4149099 (1979-04-01), Nagami
patent: 4247917 (1981-01-01), Tsang et al.
patent: 4301381 (1981-11-01), Clemen et al.
Blaser et al., "Level Converting Circuit", IBM Tech. Disc. Bull.; vol. 18, No. 11, 4-1976, p. 3722.
Leach et al., "A 1K.times.8-Bit 5V-Only Static RAM", 1978 IEEE International Solid-State Circuits Conference Digest of Technical Papers, Session IX, p. 104.

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