Boots – shoes – and leggings
Patent
1985-11-14
1989-03-21
Heckler, Thomas M.
Boots, shoes, and leggings
G06F 1306, H04L 1100
Patent
active
048150258
DESCRIPTION:
BRIEF SUMMARY
FIELD OF INVENTION
The present invention relates to an arrangement for supervising a data processing system adapted for controlling telecommunication equipment and including an address bus with the ability of transferring 2.sup.n addresses one at a time, the bus being connected to k computer elements, such as memory locations and input/output terminals, which are each accessed by an assigned binary address transferred through the bus and associated with a first category of k addresses used in data processing, there being available an address redundance consisting of 2.sup.n -k addresses of a second category, which are not used while data processing is going on.
BACKGROUND
Synchronous duplicating with comparison, multiple redundancy with majority selection, and parity checking, as well as time supervision in the form of "watch dog" and microprogrammed pointer control, are known principles for supervising a data processing system. Even if it is only partially used, duplication is very expensive in many cases. Parity checking requires a rather considerable increase in the number of components used. Pointer control and parity generation mean increased access times relative to the data processing. Time supervision results in tardy error detection.
The state of the art is dealt with, for example, in "12th Annual International Symposium on Fault-Tolerant Computing" (ISSN number 0731-3071), Session 6B On-Line Monitoring, pages 237-256.
SUMMARY OF INVENTION
Based on the fact that addresses transferred through an address bus are formed in a known manner with the aid of data transportation and data calculations, there is obtained in supervising addresses, in accordance with the invention, an indirect supervision of data processing in, for example, a stored-program controlled telecommunication system.
The inventive arrangement is characterized by an insignificant addition of components, more specifically at most 2.sup.n simple indication registers connected to the address bus, the outputs of the registers being connected to an error signal generator.
A condition for the inventive supervision principle is that the address bus has an excess capacity in relation to the number of computer elements connected thereto, i.e., such that 2.sup.n >k. This condition often exists, particularly in modern microprocessors, with n=16 and in applications of computer elements in which only a minor portion of the possible addresses is used, so that there can be thus obtained the above-mentioned two categories of addresses.
In accordance with the invention, the indication registers store the information as to the category affinity of their addresses. Since correct data processing only results in addresses of the first category, an error signal is generated from every indication obtained by the registers that an address transferred through the bus is included in the second category. The greater the address redundancy of the data processing system, the greater chance there is that the simple inventive supervision arrangement discovers data processing errors.
BRIEF DESCRIPTION OF DRAWING
The invention will next be described in detail with reference to the accompanying drawing, in which the sole FIGURE illustrates a block diagram of a preferred embodiment of the invention.
DETAILED DESCRIPTION
The drawing illustrates an address bus 3 and computer elements 2 in a conventional data processing system 1, and a supervision arrangement which includes an error signal generator 5 and indication registers 4 connected to the address bus.
In the data processing system 1, there are indicated the computer elements 2/1, 2/2 . . . 2/k, the access inputs of which are connected to an address bus 3. The address bus is capable, with the aid of n parallel lines, of transferring 2.sup.n binary address numbers one at a time, these numbers coming in, for example, from an address calculation unit (not shown). Each of the access inputs of the computer elements is connected to its own output of a conventional address decoder (not shown) included in the
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Ossfeldt Bengt E.
Palmgren Ulf E.
Heckler Thomas M.
Nguyen Viet O.
Telefonaktiebolaget LM Ericsson
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