Semiconductor device

Details Semiconductor device Semiconductor device

1987-01-30

1989-03-21

Wojciechowicz, Edward J.

357 42, 357 46, 357 55, 357 71P, 357 59, H01L 2978

Patent

active

048148415

ABSTRACT:
A semiconductor device which comprises an N channel MOS transistor deposited on a P conductivity substrate, a P channel MOS transistor mounted on said N channel MOS transistor, and a high melting metal layer interposed between the drain regions of said first and second MOS transistors in a direction perpendicular to the surface of said semiconductor device to thereby effect ohmic contact between said drain regions.

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patent: 4276688 (1981-07-01), HSU
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patent: 4476475 (1984-10-01), Naem et al.
patent: 4554572 (1985-11-01), Chatterjee
EP--A--O 096 734, (Tokyo Shibaura Denki K.K.).
IEEE Journal of Solid--State Circuits, vol. SC--17, No. 2, Apr. 1982, pp. 177-183, IEEE, New York, US.
Patents Abstracts of Japan, vol. 7, No. 58 (E--163), [1203], 10th, Mar. 1983.
Solid State Technology, vol. 24, No. 1, Jan. 1981, pp. 65-72, 92, Port Washington, New York, US.
IEEE Electron Device Letters, vol. EDL--4, No. 8, Aug. 1983, pp. 272-274.

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