Programmed logic array with two-level control timing

Details Programmed logic array with two-level control timing Programmed logic array with two-level control timing

1982-12-08

1987-04-28

Chan, Eddie P.

Boots, shoes, and leggings

364900, 34082583, 307465, G06F 928

Patent

active

046619224

ABSTRACT:
A programmed logic array (PLA) is equipped with a first master-slave shift register on the intermediate wordlines (e.g., W.sub.1, W.sub.2 . . . W.sub.n) between AND and OR planes of the PLA and a second master-slave shift register on the output lines emanating from the OR plane. In this way, since the propagation delays of both AND and OR planes are much larger than those of the registers, the speed of operation of the PLA is limited to the greater of the propagation delays of the AND and OR plane instead of the sum of these delays as in prior art.

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patent: 3974366 (1976-08-01), Hebenstreit
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patent: 4488229 (1984-12-01), Harrison
C. Mead et al., Introduction to VLSI Systems, 1980, pp. 75-84.
E. Hebenstreit et al., "High-Speed Programmable Logic Arrays in ESFI SOS Technology," IEEE Journal of Solid State Circuits, vol. SC-11, No. 3, Jun. 1976, pp. 370-374 (FIG. 3).
Pending U.S. application D. E. Blahut et al., Ser. No. 233,143, filed Feb. 10, 1981.
Pending U.S. application M. L. Harrison Case, Ser. No. 292,840, filed Aug. 14, 1981.
Pending U.S. application M. L. Harrison et al., Ser. No. 446,343, filed Dec. 2, 1982.

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