RISC microprocessor architecture implementing fast trap and exce

Details RISC microprocessor architecture implementing fast trap and exce RISC microprocessor architecture implementing fast trap and exce

1993-05-24

1995-09-05

Eng, David Y.

Boots, shoes, and leggings

364941D, 3642412, G06F 940

Patent

active

054487056

ABSTRACT:
A method for use in a microprocessor to return execution to a main program after processing an interruption to the sequential processing of instructions from the main instruction stream is disclosed. The method comprises fetching instructions from a main instruction stream to a main buffer section of a prefetch buffer and executing said fetched instructions. The method also provides for handling interruptions to the processing of the main instruction stream and allowing return to the main instruction stream without requiring prefetching of instructions already fetched. Similarly, the method provides for handling interruptions of the processing of interruptions of the processing of the main instruction stream.

REFERENCES:
patent: 3346851 (1967-10-01), Thornton et al.
patent: 3711138 (1973-11-01), Celtruda et al.
patent: 3789365 (1974-01-01), Jen
patent: 4200927 (1980-04-01), Hughes et al.
patent: 4296470 (1981-10-01), Fairchild et al.
patent: 4410939 (1983-10-01), Kawakami
patent: 4434641 (1984-02-01), Puhl
patent: 4459657 (1984-07-01), Murao
patent: 4752873 (1988-06-01), Shonai et al.
patent: 4942525 (1990-07-01), Shintani et al.
patent: 5003462 (1991-03-01), Blaner et al.
IEEE Micro, vol. 9, No. 2, Apr. 1989, Los Alamitos, Calif., U.S., pp. 26-38, Charles Melear, Motorola, Inc., The Design of the 88000 RISC Family.
Patent Abstracts of Japan, vol. 010, No. 089, Apr. 1986, & JP, A, 60 225 943 (Hitachi Seisakusho K K) 11 Nov. 1985.
IEE Transactions on Computers, vol. 37, No. 5, May 1988, New York, U.S., pp. 562-573, J. E. Smith, A. R. Pleszkun, Implementing Precise Interrupts in Pipelined Processors.
Electro Conference Record, vol. 14, 11 Apr. 1989, Los Angeles, U.S., pp. 511-519, Jelemensky, New Microcomputer Features Advanced Hardware for Real-Time Control Applications.
Computer Design, vol. 28, No. 9, 1 May 1989, Littleton, Massachusetts, U.S., pp. 86-99, Andrews, Distinctions Blur Between DSP Solutions.
A VLIW Architecture for a Trace Scheduling Compiler, Robert P. Colwell, Robert P. Nix, John J. O-Donnell, David B. Papworth, Paul K. Rodman, Multiflow Computer 175 N. Main St., Branford, Conn. 06405.
IBM Technical Disclosure Bulletin, vol. 28, No. 6, Nov. 1985, Overlap of Store Multiple Operation With Succeeding Operations Through Second Set of General Purpose Registers.
J. Hennessy & D. Patterson, Computer Architecture A Quantitative Approach, Morgan Kaufmann Publishers, Inc., 1990, (in its entirety).
V. Popescu, M. Schultz, J. Spracklen, G. Gibson, B. Lightner & D. Isaman, The Metaflow Architecture, Metaflow Technologies, Inc., Jun., 1991.
R. Weiss "Third-Generation RISC Processors", On Special Report, Mar. 30, 1992, pp. 96-108.
Johnson, Superscalar Microprocessor Design, Prentice-Hall, Inc., 1991 (in its entirety).

Affiliated with

Also associated with

Rating

RISC microprocessor architecture implementing fast trap and exce does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with RISC microprocessor architecture implementing fast trap and exce, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and RISC microprocessor architecture implementing fast trap and exce will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-480450