Method and apparatus for performing an operation mulitiple times

Details Method and apparatus for performing an operation mulitiple times Method and apparatus for performing an operation mulitiple times

1997-12-08

2000-10-17

Pan, Daniel H.

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

712213, 712217, G06F 938, G06F 930

Patent

active

061346489

ABSTRACT:
A method for operating a Reduced Instruction Set Computer (RISC) processor that executes normal RISC instructions and special RISC instructions. The method comprises the step of controlling the RISC processor to perform a single operation, using a single functional unit of the RISC processor, in response to each normal RISC instruction. The method also comprises the step of controlling the RISC processor to perform multiple operations, using multiple functional units of the RISC processor in parallel, in response to each special RISC instruction.

REFERENCES:
patent: 4766566 (1988-08-01), Chuang
patent: 5278975 (1994-01-01), Ishihata et al.
patent: 5293587 (1994-03-01), Deb et al.
patent: 5345541 (1994-09-01), Kelley et al.
patent: 5428810 (1995-06-01), Barkans
patent: 5440747 (1995-08-01), Kiuchi
patent: 5481683 (1996-01-01), Karim
patent: 5517603 (1996-05-01), Kelley et al.
patent: 5594671 (1997-01-01), Chlne et al.

Affiliated with

Also associated with

Rating

Method and apparatus for performing an operation mulitiple times does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for performing an operation mulitiple times, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for performing an operation mulitiple times will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-479526