Semiconductor memory for logic-hybrid memory

Details Semiconductor memory for logic-hybrid memory Semiconductor memory for logic-hybrid memory

1997-10-14

2000-10-17

Hoang, Huan

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523001, 365206, G11C 800

Patent

active

061341746

ABSTRACT:
This invention provides ways to intercept abnormal power signals to prevent damaging the memory in a semiconductor. To achieve this, the semiconductor memory comprises a first control signal line controlling a selection from row addresses, a second control signal line controlling a selection from column addresses, a first voltage control means cutting off the first control signal line in case that predetermined number of control signals are abnormal, and a second voltage control means cutting off the second control signal line in case that predetermined number of control signals are abnormal.

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patent: 5583816 (1996-12-01), McClure
patent: 5751645 (1998-05-01), Tsukikawa
A 500-Megabyte/s Data-Rate 4.5M DRAM, N. Kushiyama, S. Ohshima, D. Stark H. Noji, K. Sakurai, S. Takase, T. Furuyama, R. M. Barth, A. Chan, J. Dillon, J. A. Gasbarro, M. M. Griffin, M. Horowitz, T. H. Lee and Victor Lee, IEEE Journalof Solid State Circuits, vol. 28 No. 4, Apr. 1993.

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