Small size inter-processor data transfer system

Details Small size inter-processor data transfer system Small size inter-processor data transfer system

1998-06-26

1999-08-24

Harrell, Robert B.

G06F 1314

Patent

active

059435097

ABSTRACT:
In an inter-processor data transfer system between first and second processors, a first FIFO is provided for data transmitted from the first processor to be written therein, and a first register is provided for indicating whether the first FIFO is write-enabled or write-disabled. A first request circuit transmits a write-request from the first processor to the second processor by way of the first FIFO. A first notification circuit notifies the first processor if data received by the second processor by way of the first FIFO is normal or abnormal. Also, a second FIFO is provided for data transmitted from the second processor to be written therein, and a second register is provided for indicating whether the second FIFO is write-enabled or write-disabled. A second request circuit transmits a write-request from the second processor to the first processor by way of the second FIFO. A second notification circuit notifies the second processor if data received by the first processor by way of the second FIFO is normal or abnormal.

REFERENCES:
patent: 4894797 (1990-01-01), Walp
patent: 4935894 (1990-06-01), Ternes et al.
patent: 5768626 (1998-06-01), Munson et al.

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