Shadow masking process for forming source and drain regions for

Details Shadow masking process for forming source and drain regions for Shadow masking process for forming source and drain regions for

1979-02-05

1980-04-15

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

148187, 357 23, 357 59, 357 91, H01L 21265, H01L 2131, H01L 754

Patent

active

041982509

ABSTRACT:
A process for substantially reducing the overlap between a gate and the source and drain regions of a field-effect transistor is disclosed. Lateral etching of a polysilicon gate provides overhangs which extend from a gate masking member. Source/drain regions are formed by ion implanting through the gate oxide layer. A small amount of dopant is implanted through the overhangs providing a low concentration of dopant in alignment with the gate. During subsequent processing, this low concentration of dopant does not substantially diffuse as do regions of higher concentration. Significant reduction in Miller capacitance is obtained along with improved punch-through characteristics.

REFERENCES:
patent: 3823352 (1974-07-01), Pruniaux
patent: 3851379 (1974-12-01), Gutknecht
patent: 4052229 (1977-10-01), Pashley
patent: 4060427 (1977-11-01), Barile et al.
patent: 4084987 (1978-04-01), Godber
patent: 4144101 (1979-03-01), Rideout
patent: 4149904 (1979-04-01), Jones
Bratter et al., "Ion-Implanted Emitter Process . . ." IBM-TDB, 18 (1975) 1827.

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