Method for reducing the rate of interrupts in a high speed I/O c

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

395842, 395733, G06F 1300

Patent

active

059434791

ABSTRACT:
A method to reduce the rate of interrupts by the central processing unit (CPU) without any loss of interrupts. The method uses two parameters. The first parameter sets the event threshold, which is the maximum value of consecutive events allowed to occur, for example, the maximum number of received data packets before an interrupt is posted (for example, a receive interrupt) to the CPU. The second parameter sets the event time-out, which is the maximum time an event can be pending before posting an interrupt to the CPU. The second parameter is needed since the flow of events in the system is unpredictable and without the time-out limit handling of the event can be delayed indefinitely.

REFERENCES:
patent: 4599689 (1986-07-01), Berman
patent: 5452432 (1995-09-01), Macachor
patent: 5546543 (1996-08-01), Young et al.
patent: 5708814 (1998-01-01), Short et al.
patent: 5761427 (1998-06-01), Shah et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for reducing the rate of interrupts in a high speed I/O c does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for reducing the rate of interrupts in a high speed I/O c, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for reducing the rate of interrupts in a high speed I/O c will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-474846

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.