Memory device having a plurality of cell array blocks including

Details Memory device having a plurality of cell array blocks including Memory device having a plurality of cell array blocks including

1997-08-08

1999-08-24

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

36518516, 3651852, 36518909, G11C 800

Patent

active

059432861

ABSTRACT:
A memory device includes a memory cell block, a reference cell block and a comparator. The memory cell block includes a plurality of cells, and a memory bit line is connected to a selected one of the cells. The reference cell block includes a plurality of cells, and a reference bit line is connected to a predetermined number of cells which are connected in series. The comparator compares a memory signal received from the memory bit line to a reference signal received from the reference bit line to determine a bit data of the selected cell.

REFERENCES:
patent: 4912674 (1990-03-01), Matsumoto et al.
patent: 4933906 (1990-06-01), Terada et al.
patent: 5392233 (1995-02-01), Iwase
patent: 5703820 (1997-12-01), Kohno
patent: 5754475 (1998-05-01), Bill et al.

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