Non-volatile latch having PMOS floating gate memory cells

Details Non-volatile latch having PMOS floating gate memory cells Non-volatile latch having PMOS floating gate memory cells

1997-12-31

1999-08-24

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518904, 36518905, G11C 1604

Patent

active

059432683

ABSTRACT:
A non-volatile latch is disclosed which includes four PMOS floating gate memory cells arranged in a 2.times.2 matrix. Binary data values are written to the latch by the threshold voltage of the cells, where a first binary value is written by programming all the cells, and the second binary value is written by leaving all the cells in an erased state. Thus, since a program operation is required when writing only one of the binary value, high program voltages and floating gate charge times are eliminated when writing the other binary value. After a read operation in which the binary value stored in the cells is provided as output, this binary value is automatically latched in a latch circuit. In this manner, subsequent reads to the latch do not require accessing the cells.

REFERENCES:
patent: 4858185 (1989-08-01), Kowshik
patent: 5065362 (1991-11-01), Herdt et al.
patent: 5636126 (1997-06-01), Coffman et al.
patent: 5761125 (1998-06-01), Himeno
patent: 5801994 (1998-09-01), Chang et al.

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