Method for manufacturing wells for CMOS transistor circuits sepa

Details Method for manufacturing wells for CMOS transistor circuits sepa Method for manufacturing wells for CMOS transistor circuits sepa

1988-05-20

1990-03-06

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 67, 437 80, H01L 21265, H01L 2994

Patent

active

049065858

ABSTRACT:
A double well CMOS process wherein the wells are separated by insulating trenches introduced into a semiconductor substrate, the position of the insulating trench along the isotropic under-etching in a silicon oxide layer employed together with a silicon nitride layer used as a masking layer in the implantation of the well which is first implanted. The trench itself is produced by anisotropic etching with silicon oxide masks used in the well implantations as etching masks. The trench width is defined with the isotropic etching and the trench depth is defined by the anisotropic etching. In this method, both well implantations and the trench etching are carried out with only one photo-technique. The implantation of the second well and the trench etching are self-adjusting. As a result, minimum spacings between the active zones are provided, and a space saving design is possible. The method is used in LSI CMOS processes.

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Shiro Suyama et al, "A New Self-Aligned Well-Isolation Technique for CMOS Devices", IEE Transactions on Electron Devices, vol. ED-33, No. 11, Nov. 1986, pp. 1672-1677.
L. C. Parrillo et al, "Twin-Tub CMOS II-An Advanced VLSI Technology", International Electron Devices Meeting, San Francisco, California, Dec. 13-15, 1982, pp. 706-709.

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