Signal detection circuit using a plurality of delay stages with

Details Signal detection circuit using a plurality of delay stages with Signal detection circuit using a plurality of delay stages with

1997-11-19

1999-08-24

Grimm, Siegfried H.

Demodulators

Frequency shift keying or minimum shift keying demodulator

Including logic element (e.g., logic gate or flip-flop

327270, 327271, 329310, 329336, 329343, 329363, H03D 500, H03H 1126

Patent

active

059429372

ABSTRACT:
A signal detection circuit employs a delay line with edge detection logic for capturing and buffering timing information about an input signal. A plurality of comparators for comparing the input signal to different reference potentials capture amplitude information in the input signal launching bits into respective delay lines. Preferably, each delay line includes a counter for counting detected bit edges.

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