Error detecting circuit for a decoder

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Details

371 52, G06F 1100

Patent

active

049493434

ABSTRACT:
There is disclosed an error detection circuit for a decoder which includes a plurality of circuit units connected in cascade, each of the circuit units having a first and a second input node, a selection input node connected to an associated one of output terminals of the decoder, and a first and a second output node, the first and second input nodes being connected respectively to the first and second output nodes, when the selection input node receives an active level, and the first output node being controlled to take a predetermined logic level and the second output node being controlled to take a logic level responsive to the logic level at the second input node when the selection input node receives an inactive level.

REFERENCES:
patent: 3744024 (1973-07-01), Russell
patent: 4320512 (1982-03-01), Richman
patent: 4380813 (1983-04-01), Fogell

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