Dielectric etch protection using a pre-patterned via-fill capaci

Details Dielectric etch protection using a pre-patterned via-fill capaci Dielectric etch protection using a pre-patterned via-fill capaci

1998-07-10

2000-10-17

Bowers, Charles

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438386, H01L 2120

Patent

active

061331082

ABSTRACT:
Disclosed is a capacitor incorporating a material having a high dielectric constant and a method of fabricating the same. In a preferred embodiment, the bottom electrode is first deposited and patterned. An insulating diffusion barrier, such as LPCVD silicon nitride, is deposited over the bottom electrode and a via is opened in the silicon nitride to expose the bottom electrode. This via is filled with the dielectric material. In a disclosed embodiment, the dielectric material is deposited in solution form and crystallized in a high-temperature step. A top conductive layer is deposited over the dielectric material, masked and etched to form the top conductive layer. This etch may simultaneously etch any portion of the dielectric layer overflowing the contact via.

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