Improved pointer FIFO controller for converting a standard RAM i

Details Improved pointer FIFO controller for converting a standard RAM i Improved pointer FIFO controller for converting a standard RAM i

1986-03-06

1990-08-14

Williams, Jr., Archie E.

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3649261, 3649263, 3649269, 36492692, 36492781, 364955, 364957, 3649576, 3649591, 364960, 3649602, G06F 1200, G06F 1206, G06F 1208, G06F 1210

Patent

active

049493019

ABSTRACT:
A RAM buffer controller for managing the address input lines of a RAM buffer to simulate the operation of two FIFO's therein. Apparatus is included for allowing random access by a node processor in a local area network node using the RAM buffer controller to manage "transmit and receive" FIFO's to have random access to any address in the address space of the buffer without restriction to FIFO boundaries. Apparatus is also included for transmitting packets from said buffer organized into one or two linked lists. Further, apparatus is included for allowing independent initialization of any of the pointers in the RAM buffer controller which are not currently selected, and for allowing software requests for read or write access by the node processor. Further, apparatus and a method are utilized for recording status and length information at the end of a packet instead of in front thereof and for allowing any incoming packet to be flushed without saving status information or to be flushed while saving its status information.

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S. Landry, "Printer Buffer Proves RAM-Based Logic's Strength and Versatility", (Nov. 14, 1985) Electronic Design, pp. 139-144.

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