Semiconductor memory

Static information storage and retrieval – Addressing

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Details

365222, 365189, G11C 800

Patent

active

047837683

ABSTRACT:
A semiconductor memory is disclosed which comprises a memory array, an address counter designating the address of the memory array, a shift register to which the data signals read out from the memory array are preset, and a control circuit. When all the data preset to the shift register is shifted out to an external terminal, the control circuit updates the address counter. The data produced from the new address of the memory array is again preset to the shift register. The same operation is thereafter repeated, thereby producing serial data signals at the external terminal. The semiconductor memory having such a construction can read out continuous data signals without any need for external address signals.

REFERENCES:
patent: 4321695 (1982-03-01), Redwine et al.
patent: 4322635 (1982-03-01), Redwine
patent: 4564925 (1986-01-01), Onishi
patent: 4581718 (1986-04-01), Oishi

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