Method of implementation of MOS transistor gates with a high con

Details Method of implementation of MOS transistor gates with a high con Method of implementation of MOS transistor gates with a high con

1998-06-29

2000-10-17

King, Roy V.

Coating processes

Coating by vapor, gas, or smoke

Base includes an inorganic compound containing silicon or...

4272557, 4271261, 4274197, 438592, 438652, 438657, C23C 1624

Patent

active

061328065

ABSTRACT:
The present invention relates to a method of formation of an Si.sub.1-x Ge.sub.x MOS transistor gate where x is higher than 50%, on an silicon oxide gate insulator layer, consisting of depositing an Si.sub.1-y Ge.sub.y layer of thickness lower than 10 nm, where 0<y<30%; and depositing an Si.sub.1-z Ge.sub.z layer of desired thickness, where z>50%. The desired thickness ranges, for example, between 20 nm and 200 nm. x and z range, for example, between 80% and 90%.

REFERENCES:
patent: 5019882 (1991-05-01), Solomon et al.
patent: 5714777 (1998-02-01), Ismail et al.
patent: 5907789 (1999-05-01), Komatsu
Ozturk, M.C., et al., "Rapid Thermal Chemical Vapor Deposition Of Germanium and Germanium/Silicon Alloys on Silicon; New Applications In The Fabrication Of MOS Transistors", Rapid Thermal And Integrated Processing Symposium, Anaheim, CA, USA Apr. 30-May 3, 1991, 1991 Pittsburgh, PA, USA, Mater. Res. Soc, USA, pp. 223-234.

Affiliated with

Also associated with

Rating

Method of implementation of MOS transistor gates with a high con does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of implementation of MOS transistor gates with a high con, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of implementation of MOS transistor gates with a high con will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-466083