Submicron lightly doped field effect transistors

Details Submicron lightly doped field effect transistors Submicron lightly doped field effect transistors

1988-06-09

1990-08-14

Wojciechowicz, Edward J.

357 234, 357 238, 357 239, 357 42, H01L 2978

Patent

active

049491369

ABSTRACT:
A lightly doped field effect transistor has a central gate portion and source and drain portions spaced to opposite sides thereof and each having a heavily doped contact section and a sidewall spacer portion between the gate portion and contact section. Each of the source and drain portions also has a lightly doped sheath with a first portion extending to a first depth about the sides of and below the contact section, and an extension of lesser depth extending under the spacer portion to the gate portion, thus providing a stepped configuration for the sheath in cross section. The sheaths have an impurity doping concentration which is 10.sup.2 -10.sup.4 lower than the impurity doping concentration in the contact sections.

REFERENCES:
patent: 4769686 (1988-09-01), Horiuchi et al.
patent: 4771014 (1988-09-01), Liou et al.
patent: 4784965 (1988-11-01), Woo et al.
patent: 4818719 (1989-04-01), Yeh et al.
Balasubramanyam, K. et al, "Characterization of As-P Double-Diffused Drain Structure", IEDM 84, pp. 782-785.
Fu-Chieh Hsu, John Hui and Kuang Yi Chiu, "Hot-Electron Degradation in Submicron VLSI", IEDM Tech. Digest, p. 48 (1985).
Tiao yuan Huang, William W. Yao, Russel A. Martin, Alan G. Lewis, Mitsumasa Koyanagi and John Y. Chen; "A Novel Submicron LDD Transistor with Inverse-T Gate Structure", IEDM Tech. Digest, p. 742, (1986).
James S. Ni, "Modeling of Hot Electron Effects on the Device Parameters for Circuit Simulation", IEDM, p. 738 (1986).
S. Baba, A. Kita and J. Ueda, "Mechanism of Hot Carrier Induced Degradation in MOSFET's", IEDM, p. 745 (1986).
T. Noguchi, Y. Asahi, N. Ikeda, K. Maeguchi and K. Kanzaki, "Parasitic Resistance Characterization for Optimum Design of Half Micron MOSFETs," IEDM, p. 730, (1986).
Y. Hiruta, K. Maeguchi and K. Kanzaki, "Impact of Hot Electron Trapping on Half Micron PMOSFETS with P.sup.+ Poly Si Gate", IEDM, p. 718, (1986).
Paul J. Tsang, Seiki Ogura, William W. Walker, Joseph F. Shepard and Dale L. Critchlow, "Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology", IEEE Trans. on Elect. Dev., vol. ED-29, Nov. 1982, p. 590.
Seiki Ogura, Paul J. Tsang, William W. Walker, Dale L. Critchlow and Joseph F. Shepard, "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor", IEEE Trans. on Elect. Dev. vol. ED-27, p. 1359, (1980).
A. Ochoa, W. Dawes and D. Estreich, "Latch-Up Control in CMOS Integrated Circuits", IEEE Trans. in Nuclear Sci., vol. NS-26, No. 6, p. 5065 (1979).
Ronald R. Troutman, Michael J. Hargrove, "Transmission Line Modeling of Substrate Resistances and CMOS Latchup", IEEE.
A. Ochoa, Jr., P. V. Dressendorfer, "A Discussion of the Role of Distributed Effects in Latch-Up", IEEE Trans of Nuclear Sci., vol. NS-28, No. 6, p. 4992 (1981).
Bruno Ricco, Enrico Sangiorgi and Guido Ferriani, "High Holding Voltage C-MOS Technology with Lightly Doped Source and Drain Regions", IEEE, Trans of Electron Dev., vol. ED-34, No. 4, p. 810 (1987).
J. E. Schroeder, A. Ochoa, Jr. and P. V. Dressendorfer, "Latch-Up Elimination in Bulk CMOS LSI Circuits", IEEE Trans on Nuclear Sci., vol. NS-27, No. 6, p. 1735 (1980).
Eiji Takeda, Hitoshi Kume, Yoshinobu Nakagome, Tohachi Makino, Akihiro Shimizu and Shojiro Asai, "An AS.tbd.P (n.sup.+ -n.sup.-) Double Diffused Drain MOSFET for LVSI's", IEEE Trans. Electron Devices, ED 30, pp. 652-657, Jun. 1983.
Eiji Takeda, Hitoshi Kume, Toru Toyabe and Shojiro Asai, "Submicrometer MOSFET Structure for Minimizing Hot-Carrier Generation", IEEE Trans. Electron Devices, ED-29, pp. 611-618, Apr. 1982.
Eiji Takeda, Akihiro Shimizu, Hitoshi Kume and Kiyoo Itoh, "A Role of Source n.sup.- Region in LDD MOSFET's", IEEE Tran. Electron Devices, ED-33, pp. 869-870 (1986).
M. Koyanagi, A. G. Lewis, J. Zhu, R. A. Martin, T. Y. Huang and J. Y. Chen, "Investigation and Reduction of Hot Electron Induced Punchthrough (Heip) Effect in Submicron PMOSDETS", IEDM Tech. Digest, pp. 722-725 (Dec. 1986).
Christopher F. Codella and Seiki Ogura, "Halo Doping Effects in Submicron DI-LDD Device Design", IEDM Tech. Digest, 230 (Dec. 1985).
Hussein I. Hanafi, "Mosfet Over DD MOSFET", IEEE Circuits and Devices Magazine, pp. 13-15, (Nov. 1985).
Kuo-hua Lee, B. R. Jones, C. Burke, L. V. Tran, J. A. Shimer and M. L. Chen, "Lightly Doped Drain Structure for Advanced CMOS (Twin-Tub IV)," IEDM Tech. Digest, pp. 242-245 (Dec. 1985).
Chenming Hu, "Hot-Electron Effects in MOSFET's", IEDM Tech Digest, pp. 176-179 (Dec. 1983).
Fang-Shi J. Lai, L. K. Wang, Yuan Taur, Jack Yuan-Chen Sun, Karen E. Petrillo, Susan Kane Chicotka, Edward J. Petrillo, Michael R. Polcari, Thomas J. Bucelot and D. S. Zicherman, "A Highly Latchup-Immune 1-.mu.m CMOS Technology Fabricated with 1-MeV Ion Implantation and Self-Aligned TiSi.sub.2 ", IEEE Trans. Electron Dev. ED. 33, pp. 1308-1319, (Sep. 1986).
Ronald R. Troutman, "VLSI Limitations from Drain-Induced Barrier Lowering", IEEE Trans. Electron Devices, ED-26, pp. 461-468 (1979).
T. Mizuno, J. Kumagai, Y. Matsumoto, S. Sawada and S. Shinozaki, "New Degradation Phenomena by Source and Drain Hot-Carriers in Half-Micron P-MOSFETS", IEDM Tech. Digest, pp. 726-729 (1986).
Ching-Yeu Wei, J. M. Pimbley and Y. Nissan-Cohen, "Buried and Graded/Buried LDD Structures for Improved Hot-Electron Reliability", IEEE Electron Device Letters, EDL 7, pp. 380-382, (1986).
Fu-Chieh Hsu, Ping-Keung Ko, Simon Tam, Chenming Hu, and Richard S. Muller, "An Analytical Breakdown Model for Short-Channel MOSFET's", IEEE Trans. Electron Devices ED-29, pp. 1735-1740 (1982).
Tiao-Yuan Huang, William W. Yao, R. A. Martin, A. G. Lewis, M. Koyanagi and J. Y. Chen, "A New LDD Transistor with Inverse-T Gate Structure", IEEE Electron Device Letters, EDL 8, pp. 151-153 (1987).

Affiliated with

Also associated with

Rating

Submicron lightly doped field effect transistors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Submicron lightly doped field effect transistors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Submicron lightly doped field effect transistors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-465975